View S01-04_999191.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W40S01-04
SDRAM Buffer - 4 DIMM
Features
* Eighteen skew controlled CMOS outputs (SDRAM0:17) * Supports four SDRAM DIMMs * Ideal for high-performance systems designed around Intel(R)'s 440BX chip set * I2C serial configuration interface * Output skew between any two outputs is less than 250 ps * 1 to 5 ns propagation delay * DC to 133-MHz operation * Single 3.3V supply voltage * Low power CMOS design packaged in a 48-pin SSOP (Small Shrink Outline Package)
Key Specifications
Supply Voltages:....................................... VDDQ3 = 3.3V5% Operating Temperature:.................................... 0C to +70C Input Threshold: .................................................. 1.5V typical Maximum Input Voltage: ...................................VDDQ3 + 0.5V Input Frequency:............................................... 0 to 133 MHz BUF_IN to SDRAM0:17 Propagation Delay: ...... 1.0 to 5.0 ns Output Edge Rate:.................................................. >1.5 V/ns Output Skew: ............................................................ 250 ps Output Duty Cycle: .................................. 45/55% worst case Output Impedance: ........................................15 ohms typical Output Type: ................................................ CMOS rail-to-rail Part to Part Skew:........................................................700 ps
Overview
The Cypress W40S01-04 is a low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately 15 which is ideal for driving SDRAM DIMMs.
Block Diagram
SDATA SCLOCK Serial Port Device Control OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17
Pin Configuration
SSOP NC NC VDDQ3 SDRAM0 SDRAM1 GND VDDQ3 SDRAM2 SDRAM3 GND BUF_IN VDDQ3 SDRAM4 SDRAM5 GND VDDQ3 SDRAM6 SDRAM7 GND VDDQ3 SDRAM16 GND VDDQ3 SDATA [1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC VDDQ3 SDRAM15 SDRAM14 GND VDDQ3 SDRAM13 SDRAM12 GND OE [1] VDDQ3 SDRAM11 SDRAM10 GND VDDQ3 SDRAM9 SDRAM8 GND VDDQ3 SDRAM17 GND GND [1] SCLOCK
Note: 1. Internal pull-up resistor of 250K on SDATA, SCLOCK, and OE inputs (not CMOS level).
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 September 28, 1999, rev. **
W40S01-04
Pin Definitions
Pin Name SDRAM0:17 Pin No. 4, 5, 8, 9, 13, 14, 17, 18, 21, 28, 31, 32, 35, 36, 40, 41, 44, 45 11 24 25 3, 7, 12, 16, 20, 23, 29, 33, 37, 42, 46 6, 10, 15, 19, 22, 26, 27, 30, 34, 39, 43 38 1, 2, 47, 48 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within 250 ps of each other.
BUF_IN SDATA SCLOCK VDDQ3
I I/O I P
Clock Input: This clock input has an input threshold voltage of 1.5V (typ). I2C Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. I2C clock Input: The I2C data clock should be presented to this input as described in the I2C section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply.
GND
G
Ground Connection: Connect all ground pins to the common system ground plane.
OE NC
I -
Output Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW. No Connect: Do not connect.
2
W40S01-04
Functional Description
Output Control Pins Outputs three-stated when OE = 0, and toggle when OE = 1. Outputs are in phase with BUF_IN but are phase delayed by 1 to 5 ns. Outputs can also be controlled via the I2C interface. Output Drivers The W40S01-04 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W40S01-04 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W40S01-04, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W40S01-04, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W40S01-04 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Refer to Cypress clock drivers. capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15 ohms. Operation Data is written to the W40S01-04 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
3
W40S01-04
Writing Data Bytes Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 2. Data Bytes 0-2 Serial Configuration Map[2] Affected Pin Bit(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Pin No. 18 17 14 13 9 8 5 4 45 44 41 40 36 35 32 31 28 21 N/A N/A N/A N/A N/A N/A Pin Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 SDRAM15 SDRAM14 SDRAM13 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 SDRAM17 SDRAM16 Reserved Reserved Reserved Reserved Reserved Reserved Control Function Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0 Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low ------Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable) Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active Active ------Bit Control 1 Table 2 gives the bit formats for registers located in Data Bytes 0-6.
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
Note: 2. At power-up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
4
W40S01-04
How To Use the Serial Data Interface
Electrical Requirements Figure 1 illustrates electrical characteristics for the serial interface bus used with the W40S01-04. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. Although the W40S01-04 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance.
VDD
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 1. Serial Interface Bus Electrical Characteristics
5
W40S01-04
Signaling Requirements As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "start bit" as shown in Figure 3. A "stop bit" signifies that a transmission has ended. As stated previously, the W40S01-04 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 4. Sending Data to the W40S01-04 The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition).
SDATA
SCLOCK
Valid Data Bit
Change of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK Start Bit Stop Bit
Figure 3. Serial Data Bus Start and Stop Bit
6
Figure 4. Serial Data Bus Write Sequence
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 1 LSB 0 MSB
Stop Condition Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LSB
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
7 Figure 5. Serial Data Bus Timing Diagram
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD t SPSU
W40S01-04
W40S01-04
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 Unit V C C C
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%
Parameter IDD IDD Tristate VIL VIH IILEAK IILEAK VOL VOH IOL IOH CIN COUT LIN Description 3.3V Supply Current 3.3V Supply Current in Three-state Input Low Voltage Input High Voltage Input Leakage Current, BUF_IN Input Leakage Current[3]
[4]
Test Condition/ Comments BUF_IN = 100 MHz BUF_IN = 100 MHz
Min
Typ 320 5
Max
Unit mA mA
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) GND-0.3 2.0 -5 -20 IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 110 100 185 160 5 6 7 0.8 VDDQ3+0.5 +5 +5 50 V V A A mV V mA mA pF pF nH
Logic Outputs (SDRAM0:17)
Output Low Voltage Output High Voltage Output Low Current Output High Current Input Pin Capacitance (Except BUF_IN) Output Pin Capacitance Input Pin Inductance
Pin Capacitance/Inductance
Notes: 3. OE, SCLOCK, and SDATA logic pins have a 250-k internal pull-up resistor (not CMOS level). 4. Outputs loaded by 6" 60 transmission lines with 20-pF capacitors.
8
W40S01-04
AC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5% (Lump Capacitance Test Load = 30 pF)
Parameter fIN tR tF tSR tSF tEN tDIS tPR tPF tD Zo TSPP Description Input Frequency Output Rise Edge Rate Output Fall Edge Rate Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance Part to Part Skew Measured at 1.5V 1.0 1.0 1.0 1.0 45 15 700 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Test Condition Min 0 1.5 1.5 Typ Max 133 4.0 4.0 250 250 8.0 8.0 5.0 5.0 55 Unit MHz V/ns V/ns ps ps ns ns ns ns % ps
Ordering Information
Ordering Code W40S01 Document #: 38-00811 Freq. Mask Code 04 Package Name H Package Type 48-pin SSOP (300 mils)
9
W40S01-04
Package Diagram
48-Pin Shrink Small Outline Package (SSOP, 0.300 inch)
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of S01-04

	To Download S01-04 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .